This application claims benefit of priority under 35 USC xc2xa7119 to Korean Patent Application No. 2002-25515, filed on May 9, 2002, the contents of which are herein incorporated by reference in their entirety.
1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a low-voltage semiconductor memory device capable of operating at a low operating voltage (e.g., about 1.8 volts).
2. Description of the Related Art
For the convenience of portability, various electronic devices have been designed to operate by means of a battery and have a small size. In cases where the battery is used instead of an AC power source, the power consumption of the electronic device must be considered, because the power consumption is closely related to the operating time of the electronic device. Among the methods for increasing the operating time of the electronic device, one method is to increase a battery capacity. In cases where the battery capacity is increased, however, the battery must also inevitably increase in size. This hinders the miniaturization of the electronic device. Another method for increasing the operating time is lowering the operating voltage (or a power supply voltage) of the electronic device. In cases where the electronic device operates using a low power supply voltage, the operating speed of the electronic device must also be considered. Thus, when a power supply voltage of an electronic device is lowered, it is important to prevent the operating speed of the electronic device from being reduced.
An object of the present invention is to provide a low-voltage semiconductor memory device capable of improving the operating speed of the device when the power supply voltage is low.
To achieve these objects and other advantages in accordance with an embodiment of the invention, there is a provided a semiconductor memory device that includes a bit line coupled to a memory cell, a sense amplifier coupled to the bit line through a first transistor, and a discharge circuit coupled to the bit line that discharges a voltage of the bit line in response to a discharge signal, where the discharge circuit includes a second and third transistor coupled in series between the bit line and a first voltage, where a gate of the second transistor is coupled to a second voltage, and where a gate of the third transistor is coupled to the discharge signal. In this embodiment, the first voltage is a ground voltage and the second voltage is a voltage higher than a power supply voltage. The first transistor and the second transistor are high-voltage transistors of which a threshold voltage is about 0.9 V and the third transistor is a low-voltage transistor of which a threshold voltage is about 0.6 V. In this embodiment of the invention, the semiconductor memory device operates at a power supply voltage of about 1.8 V.
In accordance with another embodiment of the invention, there is provided a nonvolatile semiconductor memory device comprising a memory cell array. The memory cell array includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells. The plurality of memory cells is arranged in a matrix of word lines and bit lines. The plurality of bit lines are divided into a plurality of input/output groups. A row selection circuit selects at least one of the word lines in response to a row address signal, and a column selection circuit selects at least one of the bit lines of the input/output groups in response to a column selection signal. A discharge control circuit generates discharge signals corresponding to the bit lines of the respective input/output groups in response to a transition of the row address signal and the column selection signal. A discharge circuit discharges the voltages of the bit lines in response to the discharge signals. The discharge circuit includes a plurality of bit-line discharge units corresponding to the respective input/output groups of the bit lines. Each of the bit-line discharge units includes a first and second transistor coupled in series between the corresponding bit lines and a ground voltage. A gate of the first transistor is coupled to a voltage that is higher than a power supply voltage, and a gate of the second transistor receives a corresponding discharge signal. In this embodiment, the first transistor is a high-voltage transistor where the threshold voltage is about 0.9 V and the second transistor is a low-voltage transistor where the threshold voltage is about 0.6 V. In this embodiment of the invention, the nonvolatile semiconductor memory device operates at a power supply voltage of about 1.8 V.
In accordance with yet another embodiment of the present invention, there is provided a NOR flash memory device that includes a memory cell array divided into a plurality of memory blocks, wherein each of the memory blocks includes a plurality of word lines, a plurality of local bit lines, and a plurality of memory cells. The plurality of memory cells is arranged in a matrix of word lines and local bit lines. The plurality of local bit lines is divided into a plurality of segments. The NOR flash memory device also includes a plurality of global bit lines divided into a plurality of input/output groups, where the global bit lines correspond to the segments of the bit lines in the respective memory blocks. There is also a plurality of first column selection circuits corresponding to the memory blocks, for selecting at least one of the local bit lines of the respective segments in the corresponding memory blocks, and a second column selection circuit for selecting any one of the global bit lines of the respective input/output groups and coupling the selected global bit lines to corresponding data lines. The NOR flash memory device also includes a discharge control circuit for generating discharge signals in response to a transition of the row address signal and the column selection signal, and a discharge circuit for discharging the voltages of the global bit lines in response to the discharge signals, where the discharge circuit includes a plurality of bit-line discharge units corresponding to the respective input/output groups of the global bit lines. Each of the bit-line discharge units have a first and a second transistor coupled in series between the corresponding global bit lines and a ground voltage, where the gate of the first transistor is coupled to a voltage that is higher than a power supply voltage, and where the gate of the second transistor receives a corresponding discharge signal.